1. Field
This disclosure relates generally to memory hierarchies, and more specifically, to pipelining of tag lookups and information accesses in a cache.
2. Related Art
Accesses by a processor to addressable memory typically include calculation of an effective address, often by a memory management unit (MMU). Base/offset arithmetic is widely employed in effective address calculations and adders or similar circuits are often used. Caching techniques are also widely employed in the art to reduce effective latency for retrieval of information from memory. By providing a comparatively small and fast cache memory and managing its contents, it is possible to satisfy many memory accesses from cache memory, thereby avoiding comparatively long-latency accesses to main memory. Generally, tags (often a portion of an effective address) are employed to identify in the cache a data entry that corresponds to the desired memory access.
While caching and/or buffering techniques tend to improve the overall performance of a memory subsystem, latencies in a tag lookup and data retrieval can themselves limit performance of processor. Accordingly, improved techniques are desired.